Can Agents Design Better Chips with Higher-Level Abstractions?

Summary

This paper examines whether large language model agents can design better chips by working with higher-level abstractions instead of operating directly at register-transfer level (RTL). It compares four workflows: direct RTL design, agent-based high-level synthesis (HLS), post-compiler HLS refinement, and post-HLS RTL refinement. The authors combine agent-based HLS with post-HLS RTL refinement into a workflow called Agent-based HLS with RTL Refinement, or AHRR. Using FPGAs as a practical platform for end-to-end evaluation, they test the workflows on a diverse benchmark suite of 11 tasks. AHRR achieves a 2.6x geometric-mean speedup over direct RTL design across the suite. The case studies suggest that HLS provides abstractions that help agents apply design knowledge, while RTL refinement recovers optimization opportunities available only at a lower level. The authors state that the design-flow tradeoffs are largely independent of the target technology, although the reported evaluation uses FPGAs. Code and evaluation artifacts are available in the project repository.