AI Agent Designs a RISC-V CPU from a 219-Word Specification in 12 Hours

Summary

Verkor.io says its agentic AI system, Design Conductor, autonomously turned a 219-word requirements document into a verified, layout-ready RISC-V CPU design in 12 hours. The resulting VerCore is a five-stage, in-order, single-issue core with no caches or out-of-order execution; it met timing at 1.48 GHz on the academic ASAP7 process design kit and scored 3,261 on CoreMark. During optimization, the agent implemented a Booth-Wallace multiplier reaching 2.57 GHz and chose a one-cycle branch-penalty design after testing one- and two-cycle alternatives. The result is notable because the run covered the process from specification to GDSII layout, but it required what Verkor describes as many tens of billions of tokens. The comparison with commercial chip projects is limited: VerCore is much simpler than leading-edge processors, which can cost more than $400 million, take 18 to 36 months, and involve hundreds of engineers. VerCore has not been fabricated. Its behavior was checked in simulation with the Spike RISC-V simulator, and ASAP7 is an academic design kit rather than a production 7nm process. The paper reports that the agent sometimes misjudged task complexity and reasoned about Verilog as if it were sequential code, making timing debugging harder. Verkor estimates that five to 10 human experts would still be needed to guide a production-ready chip, while compute requirements rise nonlinearly with design complexity. The company plans to release the RTL and build scripts and demonstrate an FPGA implementation, while noting that previous AI-designed CPU projects also lacked physical silicon.