LLM Pipeline Builds Faithful, Complete Hierarchical Hardware Knowledge Graphs

Summary

Hardware datasheets contain specifications needed for component selection, system integration, and compatibility checks, but their information is fragmented across text, tables, and figures. The paper presents an automated pipeline that uses large language models to extract properties in chunks, route them hierarchically, and refine the results iteratively. Source provenance is preserved, while graph updates are applied through validated instructions and deterministic local execution. This staged design reduces the context required for each query and retains traceable intermediate representations. The authors evaluate the system on 20 datasheets covering different component types and document lengths. They measure property faithfulness and introduce inter-graph completeness to compare semantic coverage without requiring exhaustive ground truth. The proposed method achieves 98.8% property faithfulness, compared with 76.1% for one-shot processing. It fully covers 83.6% of the faithful properties found by the baseline, while the baseline covers only 10.5% of the properties produced by the proposed system. The resulting graphs are intended to support more reliable retrieval and reasoning for hardware design and verification by reducing overlooked specifications and incorrect decisions.