SK hynix Unveils Memory Roadmap to Ease AI Inference Bottlenecks

Summary

SK hynix is developing a broader memory architecture to address bottlenecks caused by rapidly growing AI inference workloads. At SEDEX 2026, Chief Development Officer Ahn Hyun said inference demand is expanding through greater task complexity, longer context windows and more requests, with the company estimating that AI infrastructure performance requirements could be about 20 times higher in 2030 than in 2026. The company argues that the challenge is no longer limited to processor performance: larger key-value caches and data movement among HBM, DRAM and SSDs can increase latency and power consumption. Its roadmap therefore combines continued HBM development, custom HBM, 3D Stacked DRAM and a new High Bandwidth Flash, or HBF, tier. HBM generations through HBM4E are intended to improve capacity, bandwidth and energy efficiency, while custom HBM adds memory controllers and customer-specific logic to the base die. 3D Stacked DRAM would place DRAM vertically above logic chips such as GPUs and NPUs, shortening the distance between memory and compute. HBF adapts HBM-related TSV stacking and high-speed I/O technologies to NAND flash, positioning it between HBM and DRAM. SK hynix is targeting roughly half the bandwidth of same-generation HBM but about 10 times its capacity, potentially reducing DRAM and SSD access for inference workloads that repeatedly read data and perform relatively fewer writes. The company plans to pursue early HBF standardization and partner across the ecosystem, while also exploring CXL and Storage-Next. Its SEDEX showcase includes server memory, enterprise SSDs, PC and mobile memory, HBM and HBF architecture displays, and an NVIDIA Vera Rubin superchip, emphasizing the company’s effort to build an integrated memory hierarchy beyond HBM alone.